I liked how yesterday’s post came out, so I figured I’d do another one. This time around, we’re talking about the number of “pins” on CPUs over the years, specifically Intel desktop chips. In the early days, CPUs came in the form of DIPs or dual in-line packages which had a row of pins on each side. As their complexity exploded, this no longer became tenable and manufacturers moved to PGAs or pin grid arrays which had a field of downward-pointing pins under the chip which plugged into a socket on the mainboard. Soon enough, the number of required connections became too much for pins to be reliable so they moved to BGA or ball grid array where balls of solder touch pads on the mainboard to make a connection. As the number of balls increased, issues with thermal and mechanic stress cropped up more and more which led to the transition to the contemporary LGA or land grid array. For an LGA socket, the CPU now only has conductive pads and it’s the connector on the mainboard that sports the pins which allows for higher manufacturing tolerances. I went through the history of the total “pin” count and created the following graph:
The trend line has a fairly good fit, typical of the information technologies. Given that Intel has been on a two-year “tick-tock” cadence with respect to new processor architectures, I thought I’d naively project the trend line and predict socket counts of future Intel microarchitectures:
- 2011 – Sandy Bridge (current): 2011 pins
- 2013 – Haswell: 2360 pins
- 2015 – Skylake: 2940 pins
- 2017 – 11? nm architecture: 3660 pins
- 2019 – 7? nm architecture: 4560 pins
I think we can reasonably be confident in the continuation of conventional CMOS Moore’s Law for this decade, but the margins of error necessarily get larger with each subsequent generation. I wonder what will replace LGA as the CPU socket of choice.